In multilayer printed circuit board (PCB) processing, the multiple layers of a PCB are typically imaged (e.g., to form circuit paths, pads, antipads, etc.), laminated and/or stacked, and then drilled to form vias. However, this process tends to introduce misalignments among the multiple layers of the PCB, which often necessitate the use of larger pads, anti-pads, and/or restrict the minimum size of pads/anti-pads that can be used. Moreover, misalignments between via pads along a multilayer PCB may also cause signal integrity problems in adjoining/adjacent conductive traces.
What is needed is a way to more accurately form via holes in a multilayer printed circuit board to permit the use of smaller pads/anti-pads and/or to provide a more consistent distance to adjoining/adjacent conductive traces along multiple layers of a multilayer PCB.